1. Field of the Invention
The present invention relates to an output circuit of a semiconductor integrated circuit device.
2. Description of the Prior Art
FIG. 12 depicts a prior art output circuit of a semiconductor integrated circuit device. Components shown in FIG. 12 include a first power source 1, ground 3, an input terminal 4 of the output circuit, an output terminal 5 of the output circuit, a PMOS transistor 40 having its gate connected to the input terminal 4, its source connected to the first power source 1, and its drain connected to the output terminal 5, and an NMOS transistor 41 having its gate connected to the input terminal 4, its source grounded, and its drain connected to the output terminal 5.
An operation of the output circuit will now be described. Voltages designated by V.sub.DD1 and V.sub.SS are applied to the first power source 1 and the ground 3, respectively, and a signal designated by V.sub.IN is applied to the input terminal 4 of the output circuit. The PMOS transistor 40 and the NMOS transistor 41 constitute a CMOS inverter gate circuit. Thus, when the input signal V.sub.IN is equal to V.sub.DD1, or over the threshold voltage of the inverter gate circuit, an output signal V.sub.OUT is is V.sub.SS. When the input signal V.sub.IN is equal to V.sub.SS, or below the threshold voltage, the output signal V.sub.OUT is V.sub.DD1.
As to a miniaturized MOS semiconductor integrated circuit device, a gate insulating film constituting a MOS transistor is very thin about 10 nm to 14 nm. Thus, the supply voltage V.sub.DD1 applied to the miniaturized MOS semiconductor integrated circuit device is lower, compared with a prior art MOS semiconductor integrated circuit device, in order to prevent dielectric breakdown of the gate insulating film or prevent the threshold voltage of the MOS transistor from being varied due to hot electrons which are developed while the MOS transistor is operated, injected into the gate insulating film, and remains as fixed electric charge in the insulating film. The output voltage V.sub.OUT from the output circuit of the semiconductor integrated circuit device shown in FIG. 12 satisfies V.sub.SS &lt;V.sub.OUT &lt;V.sub.DD1. In the event that a method of connecting an output terminal of the output circuit of the semiconductor integrated circuit device via a pull-up resistance 42 to a second power source 2 of potential VDD.sub.2 is as shown in FIG. 13, this circuitry cannot be used if V.sub.DD1 &lt;V.sub.DD2, because a P-type semiconductor and an N-type substrate of a source electrode of the PMOS transistor 40 are forwardly biased.
Another prior art semiconductor integrated circuit device is shown in FIG. 14. The device shown in FIG. 14 is generally comprised of an output circuit K20 having outputs in three states like V.sub.DD2, V.sub.SS and a high impedance condition, and an output circuit K21 having outputs in three states like V.sub.DD1, V.sub.SS and a high impedance condition, and it also includes a PMOS transistor 50 having its source connected to a power source 2 of supply voltage V.sub.DD2 and its drain connected to a bus line 55 to constitute an output stage of the output circuit K20, an NMOS transistor 51 having its source grounded to the ground potential V.sub.SS and its drain connected to the bus line 55 to constitute an output stage of the output circuit K20, a PMOS transistor 52 having its source connected to a power source 1 of supply voltage V.sub.DD1 and its drain connected to the bus line 55 to constitute an output stage of the output circuit K21, an NMOS transistor 53 having its source grounded to the ground potential V.sub.SS and its drain connected to the bus line 55 to constitute an output stage of the output circuit K21, and a pull-up resistance 54 having its one end connected to the power source 2 and the other end connected to the bus line 55 to pull up a potential of the bus line 55 to V.sub.DD2. The output circuits K20 and K21 output different voltages corresponding to logics to produce and are connected commonly to the bus line 55, and therefore, a problem as follows arises; in the event that the output circuit K21 is in the high impedance condition while the output circuit K20 outputs V.sub.DD2, a P-type semiconductor and an N-type substrate constituting a source of the PMOS transistor 52 are forwardly biased to cause current to inconveniently flow in the first power source.
As has been described, an output circuit of the prior art semiconductor integrated circuit device configured as stated above has the disadvantage that it cannot externally output a signal having a larger amplification than an internal signal of the semiconductor integrated circuit.
There is also the disadvantage that output circuits of which input signals are different in amplitude cannot be commonly connected.